Circuit arrangement for the provision of an output signal with adjustable flank pitch

ABSTRACT

Circuitry is disclosed for controlling the slope of rising and falling edges of a signal. The circuitry includes a ramp signal generator that receives an input signal and that generates a trapezoidal signal based on the input signal, and a circuit array that receives the trapezoidal signal and that generates control signals based on the trapezoidal signal. Output transistors have gates that receive a set of the control signals. The output transistors include a top transistor and a bottom transistor. The top transistor has a source connected to a supply potential and a drain connected to an output. The bottom transistor has a source connected to a reference potential and a drain connected to the output. The top transistor and the bottom transistor are gated by the control signals to control a shape of an edge of an output signal at the output.

TECHNICAL FIELD

This application relates to a circuit array for controlling the slope ofan edge of an output signal.

BACKGROUND

In integrated circuits, there is normally a need to reduceelectromagnetic interference emissions. Steep signal edges lead torelatively large emitted and conducted emissions, especially duringoperation with high-frequency, digital signals. However, to ensure thatelectronic systems do not significantly impede the operation of otherelectronic system, regulatory measures have been imposed, such as theestablishment of severity values, which are intended to guarantee theelectromagnetic compatibility (EMC) of different systems.Electromagnetic compatibility (EMC) relates to both allowableelectromagnetic emissions and required resistance to interference.

One method of reducing high-frequency signal components within thefrequency spectrum of a digital signal includes reducing the slopes ofrising and falling edges of the digital signals. Therefore, efforts havebeen made to reduce the slopes of both rising and falling signal edgesof digital signals so as to comply with EMC standards or EMCspecifications, and to guarantee reliable operation of the circuits.

In the rapid digital signal processing used today, such as in digitalsignal processors, digital signals are designed to be as fast aspossible, often in the range of a hundred picoseconds. This leads to thelarge, high-frequency spectral component of the signals. In addition,integrated circuits used in fast digital signal processing normallyoccupy a small amount of surface area on a chip and consume low powerduring operation.

In U.S. Pat. No. 6,225,844, an output stage is disclosed, which can beoperated stably with a relatively small signal slope. The specifiedoutput stage comprises two CMOS inverter stages connected in parallel,with respect to their load paths, between a reference potentialconnection and a supply potential connection. An output signal withreduced edge slope can be obtained from these inverter stages. Whereasthe first of the two input stages is directly driven by the inputsignal, an additional control circuit for influencing signal edge slopeis provided to drive the gate electrodes of the transistors of thesecond transistor inverter stage. This circuit enables the twotransistors of the second output stage to be switched on or off in acontrolled manner. Because threshold values of the transistors are usedto drive the second output stage, the principle described above can onlybe used to construct a two-stage circuit array.

A circuit array for reducing the edge slope of an output signal is alsodescribed in U.S. Pat. No. 5,140,194. In this case, several CMOSinverter output stages are connected in parallel. Delay times aregenerated to drive the various inverter stages. According to the patent,the delay times are generated with RC time constants. A disadvantage ofthis approach, however, is that it involves use of resistors havingnarrow tolerance ranges and that require a relatively large chip surfacearea. Alternatively, it is also proposed that the RC elements bereplaced with delay elements, which are also difficult to implement. Thedisadvantage remains of having to adjust the time constant individuallyfor each inverter stage on the output end, and of having to implementindividually in terms of circuit technology.

Another disadvantage shared by the above-described circuit arrays isthat the slope of the output signal is dependent on the characteristicsof the input signal.

SUMMARY

One object of this invention is to specify a circuit array for providingan output signal with an edge whose slope is adjustable, which makes itpossible to use any number of inverter stages to control the edge slopeto any degree of precision, and which further provides an output signalwhose edge slope can be adjusted independently of the signalcharacteristics of the input signal.

According to the invention, the object is achieved by a circuit arrayfor providing an output signal with adjustable edges slopes, comprising:

-   -   an input for supplying an input signal,    -   an output for accepting an output signal derived from the input        signal, whose edges slope is adjustable,    -   a ramp signal generator, which is coupled with the input of the        circuit array on the input end and provides a trapezoid signal        at its output,    -   a first pair of output transistors, the controlled paths of        which are coupled with the output of the circuit array, on the        one hand, and with a supply or reference potential connection,        on the other, and each having a control connection which is        coupled with the output of the ramp signal generator, using two        switching thresholds, and    -   a second pair of output transistors, the controlled paths of        which are coupled with the output of the circuit array, on the        one hand, and with a supply or reference potential connection,        on the other,    -   and each having a control connection which is coupled with the        output of the ramp signal generator, using two additional        switching thresholds.

Each of the pairs of output transistors preferably comprises twocomplementary transistors. These transistors are complementary withrespect to their conductivity type, for example, an n-channel and ap-channel field effect transistor is provided in each case.

The term “pair of output transistors”, in this context, refers to twooutput transistors which together form an output stage, but arepreferably not driven jointly at their control electrodes, butindependently from one another.

Preferably, three or more output stages are provided, each of whichcomprises two output transistors.

The controlled paths of the output transistors, which together form apair, are preferably connected in series. These series connections areconnected in parallel with one another. The connection nodes of thecontrolled paths of the output transistors, which together form a pair,are preferably connected to one another and to the output of the circuitarray.

According to this arrangement, the ramp signal generator controls theinput and output behavior of the first and second pair of outputtransistors via the trapezoid signal. Additional transistors, e.g.,third, fourth, etc. may be controlled by the ramp signal generator. Ashared trapezoid signal generated by the shared ramp signal generator isused for the first and second pair of output transistors, as well as forany other number of additional pairs of output transistors.

The output signal of the ramp generator is a trapezoid signal withrelatively small slope, both in its rising and in its falling signaledges.

Characteristics of the trapezoid signal, especially its edge slope, areindependent of the input signal, including the edge slope of the inputsignal.

An output signal with an adjustable edge slope can be generated withthis circuit array. Using the independently adjustable switchingthresholds of the transistors of the output signals, which areindividually switched on or off in dependence on the signal progressionof the ramp signal, a desired switching sequence and desired switchingdelays can be set precisely and independently of the progression of theinput signal of the circuit array. In particular, sequential switchingof the output transistors with the trapezoid signal can prevent theoccurrence of unwanted transverse currents. Accordingly, the presentprinciple allows for the operation of circuits in integrated circuittechnology at high signal speeds with, at the same time, relatively lowand, especially, adjustable electromagnetic emissions, because reductionof the edge slope, which is adjustable, results in the reduction of boththe high-frequency signal components in the spectrum of the digitalsignals and the related, high-frequency electromagnetic emissions. Tooperate the present circuit array with adjustable edge slope, a largenumber of expensively implemented delay elements are unnecessary.

According to an advantageous embodiment of the present circuit array,pairs of pre-drivers are provided to supply the desired switchingthresholds to couple the ramp signal generators with the first andsecond pair of output transistors. Advantageously, the switchingthresholds can be adjusted differently, both for the output transistorswithin a pair of output transistors and between the pairs of outputtransistors, and are activated during operation by the trapezoid signal.

Preferably, one pre-driver is assigned to each output transistor.

The pre-drivers are preferably formed as inverters.

To combine a necessary driver power with a small threshold, as can beprovided with some of the output transistors of the circuit array,several inverters can preferably be connected in series to form apre-driver.

According to the described principle, the inverters of the pre-driversare switched on and off sequentially by means of the trapezoid signalwith a ramp-shaped progression. The pre-drivers themselves drive theoutput transistors.

Alternatively, the pre-drivers can also be formed as Schmitt triggers,for example, or any other circuit element that provides a trapezoidalsignal.

In the described circuit array, controllable switches can be provided torapidly switch off the output transistors, which, with their controlledpaths, connect a control connection of the output transistors to thereference or supply potential connections. The controllable switchesallow a rapid shutdown of the correspondingly assigned outputtransistors and thus an especially short delay time of the output signalof the circuit array relative to the input signal. When augmented inthis manner, the circuit array is especially suitable for rapid digitalsignal processing.

The controllable switches are preferably connected via their controlelectrodes to the input of the circuit array, such as the input of theramp signal generator.

An especially rapid connection of the input of the circuit array withthe output, involving an especially short signal run time in the circuitarray, can be achieved, in accordance with a preferred embodiment of thecircuit array, in that, in a third pair of output transistors, thecontrolled paths are coupled with the output of the circuit array, onthe one hand, and with the supply or reference potential connection, onthe other, while each of the control connections of the outputtransistors of the third pair has a control connection which is coupledwith the input of the ramp signal generator to supply the input signal.

Accordingly, the third pair of output transistors is not driven by thetrapezoid signal of the ramp signal generator, but directly by the inputsignal itself.

The ramp signal generator preferably comprises a capacitive component,which, as a result of charging and discharging effects, determines thesignal ramp of the ramp-shaped signal in terms of its time progression,especially its edge slope. To this end, the ramp signal generator canhave a flip-flop structure, for example. With a ramp signal generatorconstructed in this fashion, a ramp progression of the trapezoid signalis preferably achieved which is independent of the progression of theinput signal.

According to a further embodiment of the present circuit array, thecapacitance of the capacitive component of the ramp signal generator canbe designed to be adjustable, as varactor diodes, for example.Alternatively, a combination of different, fixed capacitances can beprovided, which can be switched on and off. They can be implemented asinternal or as external capacities.

As a result, an additional means of adjusting the output signal of thecircuit array can be achieved through adjustable progression of thetrapezoid signal.

Additional details and advantageous embodiments of the invention are thesubject of the dependent claims.

In the following, the invention is described in greater detail on thebasis of several exemplary embodiments shown in the drawings:

DESCRIPTION OF THE DRAWINGS

FIG. 1 a shows, using a simplified block diagram, a first exemplaryembodiment of a circuit array according to the invention for providingan output signal with an adjustable edge slope.

FIG. 1 b shows the progression of the trapezoid signal for driving theoutput transistors shown in FIG. 1 a.

FIG. 2 shows an exemplary embodiment of a ramp signal generator shown inFIG. 1 a, using a circuit schematic.

FIG. 3 shows the time progressions of the input signal and output signalof a circuit array shown in FIG. 1 a.

FIG. 4 shows the depiction shown in FIG. 3, but based on a group ofcurves with an adjustable edge slope for the input signal relative tothe rising signal edge.

FIG. 5 a shows a further embodiment of the circuit array shown in FIG. 1a, with rapid shutoff.

FIG. 5 b shows the progression of a trapezoid signal for driving theoutput transistors shown in FIG. 5 a.

FIG. 6 a shows a further embodiment of the circuit array shown in FIG. 5a for shorter signal run times.

FIG. 6 b shows the progression of a trapezoid signal for driving theoutput transistors shown in FIG. 6 a.

FIG. 7 shows time progressions of the input signal and output signalwhen the capacitance in the ramp signal generator is changed.

DETAILED DESCRIPTION

FIG. 1 a shows a circuit array for providing an output signal B with anadjustable edge slope, comprising an input 1 for supplying an inputsignal A and an output 2 for measuring an output signal B derived fromthe input signal A, whose edge slope is adjustable. The circuit arrayalso comprises a ramp signal generator 3, the input of which is coupledwith the input 1 of the circuit array on the input end and whichprovides, at its output, a trapezoid signal C with a relativelygradually rising and gradually falling signal edge, both exhibiting aramp-shaped progression.

The output of the ramp signal generator 3 is connected to each of theinputs of a plurality of pre-drivers 4 formed as inverters. Theinverters 4 have different switching thresholds. Each of the outputs ofthe pre-drivers 4 is connected to a gate connection of a metal oxidesemiconductor (MOS) field effect transistor. Pairs of complementary MOStransistors 5, 6; 7, 8; 9, 10; 11, 12 form pairs of output transistors,such that each pair of output transistors forms an inverter stage. Eachof the inverter stages on the output end comprises a p-channeltransistor 5, 7, 9, 11, the load path of which couples a supplypotential connection 13 with the output 2 of the circuit and anN-channel-MOS transistor 6, 8, 10, 12, the load path of which connectsthe output 2 with a reference potential connection 14.

The mode of operation of the circuit shown in FIG. 1 a is explained inthe following on the basis of a signal progression of the voltage of theramp-shaped signal C, as shown in FIG. 1 b, which is supplied at theoutput end of the ramp signal generator 3, and the time progression ofwhich, especially its edge slope, is dependent on the input signal A.The trapezoid signal C sequentially switches the plurality of inverterstages 4 used as pre-drivers on and off, depending on the signal voltageand the switching thresholds of the inverters. The pre-drivers 4, inturn, drive the output transistors 5 to 12. The signal progression ofthe trapezoid signal C exhibits reversing thresholds of the inverters 4,which, for this purpose, are differently configured based on thereference symbols of the transistors 5 to 12 shown in FIG. 1 a, whichare assigned to the inverters 4, at various times t1 to t16.

In the circuit schematic shown in FIG. 1 a, the area ratios of theoutput transistors 5 to 11 as well as 6 to 12 increase from left toright, which is synonymous with the output transistors 11, 12 having thehighest current driver capacitance, and the output transistors 5, 6having the lowest current driver capacitance. Thus, the effectivetransistor areas of the output transistors are designed to be sloped inpairs relative to one another, the objective being to achieve thesmoothest possible transition in the output signal B from a low to ahigh signal level, and vice-versa.

The benefit of driving the output transistors 5 to 12 via pre-drivers 4with different switching thresholds by a shared trapezoid signal C isthat, on the one hand, a plurality of output stages, i.e., outputtransistors, can be provided, depending on the desired accuracy ofadjustment of the output signal B relative to its edge slope, and that,on the other hand, a structure with a small chip area is possible andthat, finally, the edge progression of the output signal B isindependent of that of the input signal A, because signal progression ofthe trapezoid signal C is always constant and adjustable.

The pre-driver inverters 4, which drive the output transistors 5 to 12,are designed to have different threshold voltages. Each inverter 4 isswitched on when the voltage level of the trapezoid signal 3 reaches itspreset voltage threshold value, and is switched off again when thevoltage level of the trapezoid signal C falls below this presetthreshold voltage. The threshold voltages of the inverters, which drivethe P-channel transistors 5, 7, 9, 11, are set to different values thanthe threshold voltages of those inverters 4 that drive the N-outputtransistors 6, 8, 10, 12, the purpose being to avoid transversecurrents. As explained earlier, instead of one inverter 4, a pluralityof inverters connected in series can be provided, such as threeinverters connected in series, the input-end inverter being designed togenerate the desired threshold voltage and the output-end inverter todrive the output transistor that is connected to it.

Another advantage can be achieved by designing the output-end inverter 4to be especially small relative to its transistor area. This results inan additional reduction in the edge slope of the output signal B,because the gate connection of the corresponding output transistor 5 to12 is charged relatively slowly. This forces the output transistor 5 to12 to allow an extended period of time to pass until the outputtransistor has been completely connected.

The size, that is, the transistor areas and, therefore, the drivercapacitance of the output transistor pairs 5, 6; 7, 8; 9, 10; 11, 12relative to one another are configured differently. The outputtransistor pair 5, 6 has the smallest effective transistor area. Theadjacent output transistors 7 have a larger transistor area than thetransistors 5, 6, and, in turn, the output transistors 9, 10 have alarger effective area than the output transistors 7, 8, and so on. Whenthe output signal is switched on, i.e., when there is a transition fromlow to high, the output transistors 12, 10, 8, 6 are switched offconsecutively, beginning with the largest. Then the output transistors5, 7, 9, 11 are switched off consecutively, beginning with the smallestoutput transistor. The result of connecting a smaller output transistor5, 6 is that a smaller transistor requires more time to charge anddischarge an external load capacitance than a large one. In each outputstage 5, 6; 7, 8; 9, 10; 11, 12, an external load is charged ordischarged a little further, until the output voltage at the output 2reaches the desired voltage level assigned to the corresponding logiclevel, high or low.

As mentioned earlier, the advantage of sequentially switching the outputtransistors 5 to 12 on and off is that transverse currents are reducedto a minimum. In addition to reducing the electromagnetic emission ofthe circuit, this also reduces the power consumption of the circuit.

For example, if the output signal B is to increase from a low to a highlevel, the trapezoid signal C, which drives the output transistors 5 to12 via the inverters 4, also moves from low to high. This signal rampincreases gradually over time, finally reaching the threshold voltagesof the inverters 4. The threshold voltage of the inverter 4 assigned tothe largest N-channel output transistor 12 is reached first.

This output transistor 12 switches off. Then the trapezoid signal Creaches the threshold voltage of the next smaller N-channel transistor10, and transistor 10 also switches off. In the same manner, outputtransistors 8 and 6 are switched off consecutively, until all N-channeloutput transistors are switched off. As the trapezoid signal C increasesfurther, the threshold voltage of the inverter 4 assigned to thesmallest P-channel transistor 5 is reached and output transistor 5 isswitched on. Subsequently, the threshold voltage of the next largerP-channel transistor 7 is reached, and it too switches on. Then theP-channel output transistors 9 and 11 are switched on, and the processcontinues until all P-channel output transistors are switched on. Thetotal driver capacitance that is capable of converting a load connectedto an output 2 to a high level is defined as the sum of the transistorareas of all P-channel output transistors of the circuit, and the drivercapacitance in the low state is defined as the sum of the transistorareas of all N-channel transistors.

Driving the output signal B from high to low occurs analogously. In thisprocess, first the P-channel output transistors are connected insequence and then the N-channel output transistors are connected insequence. The sequential switching on of transistors with increasingtransistor area leads to a gradually rising or falling edge of theoutput signal B. A significant advantage over known output drivers isthat, in the present principle, the peak current for charging anddischarging external loads is divided into a plurality of currentbranches, which drive a relatively low current. In addition to therelatively low load current of the individual output transistors,another advantage is that the longer amount of time needed to switch theoutput 2 leads to a lower current gradient di/dt, thereby reducing theemission of electromagnetic energy from integrated semiconductorcircuits. Another advantage lies in the reduced overshooting of theoutput signal by the drive shown.

FIG. 2 shows the circuit schematic of a possible structure of the rampsignal generator 3 from FIG. 1 a. The input signal A is supplied to theramp signal generator 3 at the input 1. The ramp signal generator 3supplies the trapezoid signal C at its output 15. The ramp signalgenerator 3 comprises two transistors 16, 17 cross-coupled with oneanother, which are formed as p-channel-MOS transistors, one end of theirload paths being coupled with the supply potential connection 13. Thetransistor 17 is connected to the reference potential connection 14through a capacitor 19. The control connection of the gate connection ofthe transistor 16 is connected to a load connection of the transistor17, while the control connection of the transistor 17 is connected to aload connection of the transistor 16. In parallel to the capacitor 19, aswitching transistor 21 is connected to its load path, its controlledpath being coupled with the input 1. In this process, the input signal Ais supplied to the control connection of the transistor 20 in unchangedform, whereas the input signal A is supplied to the control connectionof the transistor 21 in inverted form. To this end, an inverter 22 isconnected between the input 1 and the control connection of thetransistor 21.

The underlying principle of the circuit of the ramp signal generator isto charge the load capacitor 19 with a constant current. The capacitor19 does not necessarily have to be designed as external capacitors, butcan preferably be designed as a gate capacitor of MOS transistors. Thecapacitor 19 is charged by means of the PMOS transistor 17 anddischarged by means of the NMOS transistor 21, which is connected inparallel to the capacitor 19. Thus, the circuit shown in FIG. 2corresponds to a flip-flop principle. Advantageously, the ramp signalgenerator 3 exhibits no or only very little quiescent current. Currentonly flows when the capacitor 19 is charged or discharged. In addition,the ramp signal generator 3 advantageously exhibits low currentconsumption.

FIG. 3 shows, based on the progressions of the signal voltage over time,the output signal A, with a rising and a falling edge, and the outputsignal B, also on the basis of a rising and falling edges. It is evidentthat the desired effect is achieved with the present circuit, namely arelatively slow rise in the signal edge and a relatively slow fall inthe signal edge, with soft transitions and little overshoot, as well asa relatively short delay time.

FIG. 4 shows, also based on the progressions of the signal voltage overtime, a diagram of the rising edge of the input signal A and, below it,at very high chronological resolution, the rising edge of the outputsignal B according to the present principle. The signal progressions ofthe input and output signal A, B are shown as a group of curves, whereinthe pitch of the rising edge of the input signal A is selected as thegrouping parameter. It is clearly evident that, regardless of the edgeof the input signal A, the progression of the rising edge of the outputsignal B is equal in each case and, in particular, has the same edgeslope. Only the delay time is slightly dependent on the edge slope ofthe input signal A.

FIG. 5 a shows a further embodiment of the circuit shown in FIG. 1 a. Interms of its structure and advantageous mode of operation, itessentially corresponds to that shown in FIG. 1 a. In addition to thecomponents shown in FIG. 1 a, however, it has transistors for rapidlyswitching off 23, 24 the output transistors 5 to 12. Each PMOStransistor 23 for rapidly switching off the PMOS output transistors 5,7, 9, 11 is connected to the input 1 through its control connection and,through its load path, to the supply potential connection 13, on the onehand, and to the control connection of each corresponding outputtransistor 5, 7, 9, 11. In addition, an NMOS cutoff transistor 24 isassigned to each NMOS output transistor 6, 8, 10, 12, its controlledpaths being connected to the reference potential connection 14, on theone hand, and to one control input of each of the correspondingN-channel output transistors 6, 8, 10, 12, on the other, and its controlconnections being connected to the input 1 of the circuit.

An advantage offered by the further embodiment according to FIG. 5 a,with its cutoff transistors 23, 24, is that an especially low delay timeof the output signal B relative to the input signal A is achieved withrelatively little effort.

FIG. 5 b shows the progression of the trapezoid signal C for driving thecircuit shown in FIG. 5 a essentially corresponding to the signalprogression of FIG. 1 b. Only the reversing thresholds of the inverters4 assigned to the transistors 5 to 12 and the times t1 to t8 areadjusted to the further embodiment with the cutoff transistors 23, 24according to FIG. 5 a.

FIG. 6 a shows a further embodiment of the circuit according to FIG. 5a, essentially corresponding to it in terms of structure and function.Only in terms of the driving of the output transistors 5, 6, which havethe smallest transistor areas of all output transistors 5 to 12, doesFIG. 6 a differ, advantageously, from the circuit according to FIG. 5 a.In this case, the inputs of the inverters 4, which are assigned to theoutput transistors 5, 6 for the purpose of driving them, are notconnected to the output of the ramp signal generator 3, but with theinput of the ramp signal generator 3 and thus with the input 1 of thecircuit. In the circuit according to FIG. 6 a, the inverters 4 assignedto the remaining output transistors 7 to 12 are, as explained above,also connected to the output of the ramp signal generator 3. This allowsfor an even greater reduction in signal run times and phase delays ofthe output signal B relative to the input signal A.

The diagram in FIG. 6 b shows the progression of the trapezoid signal Cover time t based on the signal voltage, which essentially correspondsto the depiction of the trapezoid signal C in FIGS. 1 b and 5 b. Onlythe reversing thresholds of the inverters 4 assigned to the transistors7 to 12 and the times t1 to t6 are adjusted to the further embodimentwith cutoff transistors 23, 24 shown in FIG. 6 a, as well as to thethird output transistors 5, 6 being directly driven by the input signalA.

In the circuits shown in FIGS. 5 a and 6 a, the output transistors 5 to12 are switched on and off sequentially, as in the circuit shown in FIG.1 a. The further embodiment with the rapid cutoff transistors 23, 24shown in FIGS. 5 a and 6 a allows for rapid cutoff, so that,advantageously, a more rapid succession of the switching actions of theoutput transistors can occur, because transverse currents cannot flowbecause of the rapid cutoff.

FIG. 7 shows the signal progression of the voltage of the output signalB, using a group of curves, as a factor of the signal progression of thevoltage of the input signal A in a circuit according to FIGS. 1 a, 5 aor 6 a, based on a simulation. However, the capacitance, as the groupingparameter, of the capacitive component 19 of the ramp signal generatorshown in FIG. 2 is varied. The output signal B with the steepest edgeslope is accepted at the smallest capacitance and that with the smallestedge slope at the largest capacitance. Between these extremes, thecapacitance was increased in discrete steps.

1. Circuitry comprising: a ramp signal generator that receives an inputsignal and that generates a trapezoid trapezoidal signal based on theinput signal; a circuit array that receives the trapezoidal signal andthat generates control signals based on the trapezoidal signal; a firstof output transistors having gates that receive a first set of thecontrol signals, the first output transistors comprising a first toptransistor and a first bottom transistor, the first top transistorhaving a source connected to a supply potential and a drain connected toan output, the first bottom transistor having a source connected to areference potential and a drain connected to the output, the first toptransistor and the first bottom transistor being gated by the first setof control signals to control a shape of an edge of an output signal atthe output; and second output transistors having gates that receive asecond set of the control signals, the second output transistorscomprising a second top transistor and a second bottom transistor, thesecond top transistor having a source connected to the supply potentialand a drain connected to the output, the second bottom transistor havinga source connected to the OF reference potential and a drain connectedto the output, the second top transistor and the second bottomtransistor being gated by the second set of control signals to controlthe shape of the edge of the output signal.
 2. The circuitry of claim 1,wherein the circuit array comprises pre-drivers, and each of the firstand second output transistors has a switching threshold that is met by acontrol signal provided by one of the pre-drivers.
 3. The circuitry ofclaim 2, wherein the pre-drivers comprise at least one of inverters anda circuit element that produces an adjustable switching threshold. 4.The circuitry of claim 1, further comprising: controllable switches toswitch off the first and second output transistors by connecting thegates of the first and second output transistors to either the referencepotential or the supply potential.
 5. The circuitry of claim 4, whereineach of the controllable switches comprises a transistor having a gatethat is connected to input signal.
 6. The circuitry of claim 1, furthercomprising: third output transistors having gates that receive aninversion of the input signal, the third output transistors comprising athird top transistor and a third bottom transistor, the third toptransistor having a source connected to the the supply potential and adrain connected to the output, the third bottom transistor having asource connected to the reference potential and a drain connected to theoutput, the third top transistor and the third bottom transistor beinggated by the inversion of the input signal.
 7. The circuitry of claim 1,wherein the trapezoidal signal has an edge with a shape that isindependent of the input signal.
 8. The circuitry of claim 7, whereinthe ramp signal generator comprises a capacitive component forcontrolling a shape of rising and falling edges of the of thetrapezoidal signal.
 9. The circuitry of claim 8, wherein the capacitanceof the capacitive component is adjustable.
 10. The circuitry of claim 1,wherein areas of the first and second output transistors are ofdifferent sizes.
 11. The circuitry of claim 1, wherein the shapecomprises a slope of the edge of the ouput signal.
 12. The circuitry ofclaim 11, wherein the edge comprises at least one of a rising edge ofthe output signal and a falling edge of the output signal.
 13. Circuitryfor adjusting a slope of an edge of an output signal, the circuitrycomprising: a ramp signal generator that outputs a trapezoidal signal;drivers that respond to the trapezoidal signal by outputting controlsignals, the drivers having different switching thresholds; a set of toptransistors, each of the top transistors comprising a gate that receivesa control signal from a corresponding driver, a source connected to asupply potential, and a drain connected to an output; and a set ofbottom transistors, each of the bottom transistors comprising a gatethat receives a control signal from a corresponding driver, a sourceconnected to a reference potential, and a drain connected to the output;wherein, at a rising edge of the trapezoidal signal, driverscorresponding to the bottom transistors output control signals tosequentially deactivate the bottom transistors and then driverscorresponding to the top transistors output control signals tosequentially activate the top transistors.
 14. The circuitry of claim13, wherein the bottom transistors are sequentially deactivated startingwith a transistor having a largest effective area and proceeding to atransistor having a smallest effective area.
 15. The circuitry of claim13, wherein the top transistors are sequentially activated starting witha transistor having a smallest effective area and proceeding to atransistor having a largest effective area.
 16. The circuitry of claim13, wherein, at a falling edge of the trapezoidal signal, driverscorresponding to the top transistors output control signals tosequentially deactivate the top transistors and then driverscorresponding to the bottom transistors output control signals tosequentially activate the bottom transistors.
 17. The circuitry of claim16, wherein the bottom transistors are sequentially activated startingwith a bottom transistor having a smallest effective area and proceedingto a bottom transistor having a largest effective area.
 18. Thecircuitry of claim 16, wherein the top transistors are sequentiallydeactivated starting with a top transistor having a largest effectivearea and proceeding to a top transistor having a smallest effectivearea.
 19. The circuitry of claim 13, wherein the top transistorscomprise P-channel transistor and the bottom transistors compriseN-channel transistors.
 20. The circuitry of claim 13, wherein the bottomtransistors comprise P-channel transistor and the top transistorscomprise N-channel transistors.